As shown in FIG. 6, in an arrangement example of a conventional display module, a plurality of source drivers 100 and gate drivers 200 composed of an LSI (Large Scale Integrated Circuit), which are mounted on TCPs (Tape Carrier Packages) 300, are mounted on a liquid crystal panel 400 and a flexible substrate 500 as source drivers S and gate drivers G. Note that, the TCP is a generic name of a thin package in which an LSI element is supported by being pasted with a tape film and the like.
The plurality of source drivers S drive source bus lines (not shown) on the liquid crystal panel 400, whereas the plurality of gate drivers G drive gate bus lines (not shown) on the liquid crystal panel 400.
Furthermore, a terminal group of the source drivers S and the gate drivers G on a side of the liquid crystal panel 400 are electrically connected to a terminal group (not shown) composed of ITO (Indium Tin Oxide) on the liquid crystal panel 400 via wiring formed on the TCPs 300. These terminal groups are electrically connected by means of, for example, thermo-compression bonding via an ACF (Anisotropic Conductive Film).
On the other hand, a terminal group of the source drivers S and the gate drivers G on a side of the flexible substrate 500 are electrically connected to wiring provided on the flexible substrate 500 via the wiring formed on the TCPs 300, by means of the ACF or soldering.
As described above, a controller circuit 600 supplies display data signals (three kinds of signals of R·G·B) to the source drivers S, and supplies kinds of control signals or power supplies (GND, VCC) to the source drivers S and the gate drivers G via the wiring on the flexible substrate 500 and the wiring on the TCPs 300.
By the way, in the arrangement example shown in FIG. 6, a total of eight source drivers S are provided, namely a first source driver (1) through an eighth source driver S(8). On the other hand, a total of two gate drivers G are provided, namely a first gate driver G(1) and a second gate driver G(2).
The first source driver S(1) through the eighth source driver S(8), having an identical arrangement, receive the display data signals R·G·B, a start pulse signal SSPI, and a clock signal SCK, which are respectively outputted from the controller circuit 600. On the other hand, the first gate driver G(1) and the second gate driver G(2), having an identical arrangement, receive a clock signal GCK, and a start pulse signal GSPI from the controller circuit 600.
FIG. 7 shows an enlarged view of the controller circuit 600 which outputs kinds of signals. When the liquid crystal panel 400 has 1024 pixels (the source side)×3 (R·G·B)×768 pixels (the gate side), for example, the first source driver S(1) through the eighth source driver S(8) respectively display 26=64 tone gradations. Further, the first source driver S(1) through the eighth source driver S(8) respectively drive 128 pixels×3 (R·G·B).
Furthermore, as shown in FIG. 8, the source driver 100 includes a shift register circuit 110, a data latch circuit 120, a sampling memory circuit 130, a hold memory circuit 140, a reference voltage generating circuit 150, a DA converter circuit 160, and an output circuit 170. Note that, in the following explanation, it is assumed that the source driver 100 shown in FIG. 8 is the first source driver S(1) (see FIG. 6).
The shift register circuit 110 shifts the start pulse signal SSPI supplied to an input terminal SSPin, in synchronism with the clock signal SCK supplied to an input terminal SCKin of the source driver 100. Note that, the start pulse signal SSPI is a signal that is outputted from a terminal SSPI (see FIG. 7) of the controller circuit 600, and is synchronized with a horizontal synchronizing signal of the display data signals R·G·B. Further, the clock signal SCK is a signal outputted from an input terminal for the clock signal SCK (see FIG. 7) in the controller circuit 600.
Furthermore, the start pulse signal SSPI shifted by the shift register circuit 110 is transferred to a shift register circuit (not shown) in the eighth source driver S(8) of the eighth stage.
The data latch circuit 120 temporarily latches respective 6-bit display data signals R·G·B, which are serially sent respectively to input terminals R1in to R6in, input terminals G1in to G6in, and input terminals B1in to B6in, in synchronism with a rising edge of a signal/SCK, which is an inverted signal of the clock signal SCK, and then sends the respective 6-bit display data signals R·G·B to the sampling memory circuit 130. Note that, the display data signals R·G·B are signals which are outputted from terminals R1 to R6, terminals G1 to G6, and terminals B1 to B6 of the controller circuit 600.
The sampling memory circuit 130 samples the display data signals (a total of 18 bits of respective 6-bit R·G·B), which are sent in a manner of time division from the data latch circuit 120, and stores the respective display data signals until collecting the display data signals of a horizontal synchronization period. Then the respective display data signals are sent to the hold memory circuit 140.
The hold memory circuit 140 latches the display data signals, which are supplied from the sampling memory circuit 130, when the display data signals R·G·B of a horizontal synchronization period are collected in synchronism with a latch signal LS (a horizontal synchronizing signal). Furthermore, the hold memory circuit 140 holds the display data signals of one horizontal synchronization period until the next latch signal LS is supplied, and outputs the display data signals to the DA converter circuit 160 later described.
The reference voltage generating circuit 150 generates 64 levels of voltages, which are used for displaying tone gradations, by a resistance division circuit, for example, in accordance with a reference voltage which is outputted from terminals Vref 1 to Vref 9 (FIG. 7) of the controller circuit 600 and supplied to terminals Vref1 to Vref9 of the source driver 100.
The DA converter circuit 160 selects one of the 64 levels of voltages in accordance with the respective 6-bit display data signals (digital) of RGB supplied from the hold memory circuit 140. Thus, the conversion of a digital signal into an analog signal is carried out, and the analog signal thus converted is sent to the output circuit 170.
The output circuit 170 amplifies or converts to low impedance output, the analog signal selected by the DA converter circuit 160, and outputs the amplified or converted analog signal to the source bus line terminals (not shown) of the liquid crystal panel 400 via output terminals Xo-1 to Xo-128, Yo-1 to Yo-128 and Zo-1 to Zo-128. Note that, the output terminals Xo-1 to Xo-128, Yo-1 to Yo-128 and Zo-1 to Zo-128 respectively correspond to the respective display data signals R·G·B, and respectively have 128 terminals.
Furthermore, a terminal VCC and a terminal GND of the source driver 100 are provided for supplying power supplies, which are connected with the terminal VCC and the terminal GND of the controller circuit 600. The terminal VCC receives a power supply voltage, whereas the terminal GND receives a ground potential.
As described above, each of the source drivers 100 for displaying 64 tone gradations outputs the analog voltage to the liquid crystal panel 400 in accordance with the display data signals, thereby displaying 64 tone gradations. Note that, the gate driver 200 basically has a same arrangement as the source driver 100, thus their explanation is omitted here.
Furthermore, a technique is generally known for improving timing of receiving the display data signals as explained below.
Namely, as shown in FIG. 9, two systems (two ports) of the input terminals for the 6-bit display data signals R·G·B are provided as RA1in to RA6in, GA1in to GA6in and BA1in to BA6in, as well as RB1in to RB6in, GB1in to GB6in, and BB1in to BB6in, and the display data signals are separated into odd number data and even number data. Then the separated display data signals are received in synchronism with a rising edge or a falling edge of the clock signal having an identical frequency with the display data signals which are separated into two systems. This reduces a frequency of the clock signal for receiving the display data signals, thereby improving the timing of receiving the display data signals.
However, as a recent display module has a larger screen and a higher definition, following problems occur.
For example, the source driver for displaying 64 tone gradations requires a total of 18 data (6 bits×R·G·B) corresponding to RGB. 1024×768 pixels of XGA (extended graphics array) panel receives display data signals having a quite high frequency of 65 MHz. 1280×102 pixels of SXGA (super extended graphics array) having higher definition receives display data signals having a higher frequency of 95 MHz.
For this reason, when an image is to be displayed in higher definition, the sampling memory circuit is required to quickly store in a manner of time division the display data signals having such a high frequency as described above, after having been latched by the data latch circuit. However, when data having a high frequency is received in synchronism with the display data signals, a problem occurs that it becomes difficult to set the timing of receiving data (a data setup/hold time).
Furthermore, it becomes difficult to obtain a sufficient duty ratio (a ratio of a high period to a low period) of the data transfer clock in the source driver, thereby causing a problem of degrading image quality.
Note that, in a technique to separate the display data signals into two ports as shown in FIG. 9, a method can be considered to increase the number of ports for separating so as to respond to the display data signals having a higher frequency.
However, wiring required for the respective separated ports enlarges the source driver, and thus increases a size of the flexible substrate, thereby causing a problem that the display module becomes larger.